PIC18F1230T-I/SO【PDF 146/318 页】IC PIC MCU FLASH 2KX16 18SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3871

142页 143页 144页 145页 [146页]147页 148页 149页 150页

PIC18F1230/1330

2009 Microchip Technology Inc.

DS39758D-page 23

3.4

RC Oscillator

For timing insensitive applications, the “RC” and

“RCIO” device options offer additional cost savings.

The actual oscillator frequency is a function of several

factors:

supply voltage

values of the external resistor (REXT) and

capacitor (CEXT)

operating temperature

Given the same device, operating voltage and

temperature and component values, there will also be

unit-to-unit frequency variations. These are due to

factors such as:

normal manufacturing variation

difference in lead frame capacitance between

package types (especially for low CEXT values)

variations within the tolerance of limits of REXT

and CEXT

In the RC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 3-5 shows how the R/C combination is

connected.

FIGURE 3-5:

RC OSCILLATOR MODE

The RCIO Oscillator mode (Figure 3-6) functions like

the RC mode, except that the OSC2 pin becomes an

additional general purpose I/O pin. The I/O pin

becomes bit 6 of PORTA (RA6).

FIGURE 3-6:

RCIO OSCILLATOR MODE

3.5

PLL Frequency Multiplier

A Phase Locked Loop (PLL) circuit is provided as an

option for users who wish to use a lower frequency

oscillator circuit or to clock the device up to its highest

rated frequency from a crystal oscillator. This may be

useful for customers who are concerned with EMI due

to high-frequency crystals or users who require higher

clock speeds from an internal oscillator.

3.5.1

HSPLL OSCILLATOR MODE

The HSPLL mode makes use of the HS mode oscillator

for frequencies up to 10 MHz. A PLL then multiplies the

oscillator output frequency by 4 to produce an internal

clock frequency up to 40 MHz. The PLLEN bit is not

available in this oscillator mode.

The PLL is only available to the crystal oscillator when

the FOSC3:FOSC0 Configuration bits are programmed

for HSPLL mode (= 0110).

FIGURE 3-7:

PLL BLOCK DIAGRAM

(HS MODE)

3.5.2

PLL AND INTOSC

The PLL is also available to the internal oscillator block

in selected oscillator modes. In this configuration, the

PLL is enabled in software and generates a clock

output of up to 32 MHz. The operation of INTOSC with

the PLL is described in Section 3.6.4 “PLL in INTOSC

Modes”

OSC2/CLKO

CEXT

REXT

PIC18FXXXX

OSC1

FOSC/4

Internal

Clock

VDD

VSS

Recommended values: 3 k

REXT 100 k

CEXT > 20 pF

CEXT

REXT

PIC18FXXXX

OSC1

Internal

Clock

VDD

VSS

Recommended values: 3 k

REXT 100 k

CEXT > 20 pF

I/O (OSC2)

RA6

VCO

Loop

Filter

Crystal

Osc

OSC2

OSC1

PLL Enable

FIN

FOUT

SYSCLK

Phase

Comparator

HS Oscillator Enable

(from Configuration Register 1H)

HS Mode

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式